... options for lead free joints. We report on two sets of systematic experiments. The first addressed the performance of combinations of underfills, no-clean fluxes, and solder alloys in a JEDEC level 3 moisture sensitivity test. The second one involved thermal shock testing of flip chip assemblies...

... of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface...

... stages: 1) formation of a surface (blind) microcrack (or a grid of surface microcracks) using a double thermal shock method, and 2) splitting the cracked wafer into chips along the microcrack contour by applying small bending stresses. The emphasis was given to splitting of thin wafers with the thickness...

... to the corresponding fatigue life of experimental test through least-squares curves fitting to determine the empirical coefficients in the Coffin-Manson equation. As a demonstrator, the solder joint fatigue in wafer level chip scale packaging under thermal shock loading was analyzed. An appropriate constitutive...

...). After the CBGA modules were placed on PCBs, the specimens were divided into two groups, and reflowed in nitrogen and compressed air separately. Properties of the six groups of assemblies, such as shear strength, bending fatigue life, thermal shock cycles, and vibration fatigue life, were tested to find...