The occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper, the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface has been studied under monotonic as well as thermomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination.
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e-mail: sakethraman.mahalingam@ge.com
e-mail: suresh.sitaraman@me.gatech.edu
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December 2008
Research Papers
Theoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials
Saketh Mahalingam,
e-mail: sakethraman.mahalingam@ge.com
Saketh Mahalingam
General Electric Global Research Center
, Bangalore 560066, India
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Ananth Prabhakumar,
Ananth Prabhakumar
General Electric Global Research Center
, Niskayuna, NY 12309
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Sandeep Tonapi,
Sandeep Tonapi
General Electric Global Research Center
, Niskayuna, NY 12309
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Suresh K. Sitaraman
Suresh K. Sitaraman
Computer Aided Simulation of Packaging Reliability (CASPaR) Laboratory,
e-mail: suresh.sitaraman@me.gatech.edu
G. W. Woodruff School of Mechanical Engineering
, Atlanta, GA 30332
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Saketh Mahalingam
General Electric Global Research Center
, Bangalore 560066, Indiae-mail: sakethraman.mahalingam@ge.com
Ananth Prabhakumar
General Electric Global Research Center
, Niskayuna, NY 12309
Sandeep Tonapi
General Electric Global Research Center
, Niskayuna, NY 12309
Suresh K. Sitaraman
Computer Aided Simulation of Packaging Reliability (CASPaR) Laboratory,
G. W. Woodruff School of Mechanical Engineering
, Atlanta, GA 30332e-mail: suresh.sitaraman@me.gatech.edu
J. Electron. Packag. Dec 2008, 130(4): 041005 (5 pages)
Published Online: November 17, 2008
Article history
Received:
July 25, 2005
Revised:
March 19, 2008
Published:
November 17, 2008
Citation
Mahalingam, S., Prabhakumar, A., Tonapi, S., and Sitaraman, S. K. (November 17, 2008). "Theoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials." ASME. J. Electron. Packag. December 2008; 130(4): 041005. https://doi.org/10.1115/1.3010378
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