The results of this study demonstrate the viability of a low cost maskless process for the fabrication of ultra-fine pitch solder bumps. The fabricated solder bump arrays have a pitch and diameter of 120 and 70 μm, respectively. Widely used eutectic 63Sn37Pb and lead-free 95.5Sn3.8Ag0.7Cu solders were used to form the bumps. No solder bridging was observed between adjacent bumps, and the solder bumps exhibited good dimensional uniformity. The solder bump to aluminum (Al) pad bond integrity was found to be excellent, as evidenced by the high stress to failure. The failure mode is predominately Al pad lift-off indicating a robust solder bump-pad joint.

Issue Section:
Technical Papers
Keywords:
fine-pitch technology, soldering, flip-chip devices, integrated circuit interconnections, integrated circuit packaging, aluminium, microassembling
Topics:
Flip-chip devices, Manufacturing, Solders, Flip-chip
1.
Tumala, R. R., and Rymaszewski, E. J., 1989, Microelectronics Packaging Handbook, Chapman & Hall, New York.
2.
Tsunoi, K., Kusagaya, T., and Kira, T., 1995, “Flip Chip Mounting Using Stud Bumps and Adhesive for Encapsulation,” Flip Chip Technologies, pp. 357–366, McGraw-Hill, New York.
3.
Kaga, Y., 1997, “New Stud Bumping Technology Using Copper Wire,” Proc. Surface Mount International, San Jose, CA, pp. 273–277.
4.
Semiconductor Industry Association Roadmap, International Technology Roadmap for Semiconductors, 1999, International Sematech, Austin, Texas.
5.
Li
,
L.
, and
Thompson
,
P.
,
2000
, “
Stencil Printing Process Development for Flip Chip Interconnect
,”
IEEE Trans. Components, Packaging and Manufacturing Technology, Part C
,
23
, pp.
165
–
170
.
6.
Zama, S., Baldwin, D. F., Hikami, T., and Murata, H., 2000, “Flip Chip Interconnect Systems Using Wire Stud Bumps and Lead Free Solder,” Proc. Electronic Components and Technology Conference, pp. 1111–1117.
7.
Kloeser, J., Heinricht, K., Kutner, K., Jung, E., Ostmann, A., Zakel, E., and Reichl, H., 1997, Proc. Electronic Components and Technology Conference, pp. 254–264.
8.
Kang, S. K., Horkans, J., Andricacos, P. C., Carruthers, R. A., Cotte, J., Datta, M., Gruber, P., Harper, J. M. E., Kwietniak, K., Sambucetti, C., Shi, L., Brouillette, G., and Danovitch, D., 1999, Proc. Electronic Components and Technology Conference, pp. 283–288.
9.
Elenius, P., Leal, L., Ney, J., Stepniak, D., and Shing, Yeh., 1999, Proc. Electronic Components and Technology Conference, pp. 260–265.
10.
American Fine Wire Packaging Materials, 2001, “AW6 Gold Wire for Chip and Wafer Level Bumping Applications.”
11.
Hotchkiss, G., Amador, G., Jacobs, L., Stierman, R., Dunford, S., Hundt, P., Beikmohamadai, A., Cairncross, A., Gantzhorn, O., Quinn, B., and Saltzberg, M., 1998, Proc. Electronic Components and Technology Conference, pp. 434–441.
12.
Lau, J. H., and Pao, Y. H., 1997, Solder Relability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York.
Copyright © 2003
 by ASME
You do not currently have access to this content.