Fracture mechanics is applied to flip-chip BGA design to avert die cracking from its backside. Fracture mechanics is integrated with the finite element analysis (FEA) and design of virtual experiments (virtual DOE) to analyze the effects of location and length of a die crack, and the effects of some key material properties and package dimensions on die cracking of flip-chip BGA. The stress intensity factor (SIF) and the strain energy release rate (ERR) are taken as the design indices. The FEA is used to calculate the fracture parameters, and the virtual DOE is employed to determine contributions of each design parameter to die cracking and their acceptable design windows. The investigation consists of two parts. The first is relations of length and location of a die crack with the fracture parameters. The relations are established through sweeping along crack length for a crack located at the center of the die backside, and along the die backside surface. The critical crack length is determined for a specific design. The second is the virtual DOE based on fracture mechanics. Several key material properties and package dimensions are used as the design inputs. The main effects and interactions of these design parameters to die cracking are calculated. Based on it, some generic design guidelines are made. It is concluded that substrate and die thicknesses are the two most significant factors to die cracking of flip-chip BGA. Increasing substrate thickness and reducing die thickness are the most effective measures to design a package with high resistance to die cracking.
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March 2001
Technical Papers
Flip-Chip BGA Design to Avert Die Cracking
J.-B. Han
J.-B. Han
Agilent Technologies, Imaging Electronics Division, Hardcopy Electronics Operation, 2 Corporation Road, Corporation Place 05-01, Singapore 618494, Singapore
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J.-B. Han
Agilent Technologies, Imaging Electronics Division, Hardcopy Electronics Operation, 2 Corporation Road, Corporation Place 05-01, Singapore 618494, Singapore
Contributed by the Electrical and Electronic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EEPD October 29, 1999. Associate Editor: B. Michel.
J. Electron. Packag. Mar 2001, 123(1): 58-63 (6 pages)
Published Online: October 29, 1999
Article history
Received:
October 29, 1999
Citation
Han, J. (October 29, 1999). "Flip-Chip BGA Design to Avert Die Cracking ." ASME. J. Electron. Packag. March 2001; 123(1): 58–63. https://doi.org/10.1115/1.1329130
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