A novel and reliable wafer level chip scale package (WLCSP) is investigated in this paper. It consists of a copper conductor layer and two low cost dielectric layers. The bump geometry consists of the eutectic solder, the copper core, and the under bump metallurgy. Nonlinear time-temperature-dependent finite element analyses are performed to determine the shear stress, shear creep strain, shear stress and shear creep strain hysteresis loops, and creep strain energy density of the corner solder joint. The thermal-fatigue life of the corner solder joint is then predicted by the averaged creep strain energy density range per cycle and a linear fatigue crack growth rate theory. The WLCSP solder bumps are also subjected to shear test. Finally, the WLCSP solder joints are subjected to both mechanical shear and thermal cycling tests. [S1043-7398(00)01004-5]
Skip Nav Destination
Article navigation
December 2000
Technical Papers
Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis
John H. Lau, ASME Fellow,
John H. Lau, ASME Fellow
Express Packaging Systems, Inc., 1137 San Antonio Road, Palo Alto, CA 94303
Search for other works by this author on:
S.-W. Ricky Lee, ASME Member,
S.-W. Ricky Lee, ASME Member
Express Packaging Systems, Inc., 1137 San Antonio Road, Palo Alto, CA 94303
11
Search for other works by this author on:
Chris Chang
Chris Chang
Express Packaging Systems, Inc., 1137 San Antonio Road, Palo Alto, CA 94303
Search for other works by this author on:
John H. Lau, ASME Fellow
Express Packaging Systems, Inc., 1137 San Antonio Road, Palo Alto, CA 94303
S.-W. Ricky Lee, ASME Member
11
Express Packaging Systems, Inc., 1137 San Antonio Road, Palo Alto, CA 94303
Chris Chang
Express Packaging Systems, Inc., 1137 San Antonio Road, Palo Alto, CA 94303
Contributed by the Electrical and Electronic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EEPD Aug. 15, 1999; revised manuscript received May 29, 2000. Associate Technical Editor: Tony Rafanelli.
J. Electron. Packag. Dec 2000, 122(4): 311-316 (6 pages)
Published Online: May 29, 2000
Article history
Received:
August 15, 1999
Revised:
May 29, 2000
Citation
Lau, J. H., Lee, S. R., and Chang, C. (May 29, 2000). "Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis ." ASME. J. Electron. Packag. December 2000; 122(4): 311–316. https://doi.org/10.1115/1.1289769
Download citation file:
Get Email Alerts
Anand Model Constants of Sn–Ag–Cu Solders: What Do They Actually Mean?
J. Electron. Packag (June 2025)
Sequential Versus Concurrent Effects in Combined Stress Solder Joint Reliability
J. Electron. Packag (June 2025)
Related Articles
Reliability Prediction of Area Array Solder Joints
J. Electron. Packag (December,2003)
Measurement of Creep and Relaxation Behaviors of Wafer-Level CSP Assembly Using Moire´ Interferometry
J. Electron. Packag (June,2003)
Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board
J. Electron. Packag (June,2002)
Coarsening in BGA Solder Balls: Modeling and Experimental Evaluation
J. Electron. Packag (September,2003)
Related Proceedings Papers
Related Chapters
Polycrystalline Simulations of In-Reactor Deformation of Zircaloy-4 Cladding Tubes during Nominal Operating Conditions
Zirconium in the Nuclear Industry: 20th International Symposium
Division 5—High Temperature Reactors
Companion Guide to the ASME Boiler and Pressure Vessel Codes, Volume 1, Fifth Edition
Division 5—High Temperature Reactors
Online Companion Guide to the ASME Boiler & Pressure Vessel Codes